Solder columns grid arrays (CGA) have been used as a package in the IC industry. The high aspect ratio of the solder columns, for instance, typically 4 to 1, allows the CGA package to tolerate significant coefficient of thermal expansion (CTE) mismatches between the package and the electronic substrate. Conventionally, a high melting point solder material such as a 90Pb/10Sn solder having a 300.degree. C. melting temperature has been used to make connections directly to a ceramic CGA package. Since the melting temperature of the high melting point solder material exceeds the processing temperature of some subsequently used materials, the process of attaching the solder columns has to be carried out in the early stage of the manufacturing process. The solder columns formed in the early stage are therefore prone to mechanical damages such as bending, flaring, etc, through the remaining manufacturing process.
More recently, a new technique of attaching the 90Pb/10Sn solder columns with a lower temperature eutectic solder, such as 37Pb/63Sn with a melting temperature of 183.degree. C., has been developed to attach the solder columns at the end of the manufacturing process and thus, reducing the probability for damage. The lower temperature solder is applied to one end of the high temperature solder columns by means of applying a solder paste material of 37Pb/63Sn.
In the conventional process, known as column last attached solder process (CLASP), described in U.S. patent application Ser. No. 09/014,804, assigned to the common assignee of the present application, solder columns are attached at the end of the manufacturing cycle by utilizing pre-fabricated solder columns made by cutting extruded solder wire to a specific length. The conventional process is therefore extremely labor intensive since it involves a process of precision wire extrusion, wire cutting, as well as storage and packaging. The conventional process further involves the step of loading the solder columns into a graphite fixture positioned on a vibration table. The loading process is again time consuming and is prone to problems. For instance, during the wire cutting or shipping/handling, the thin solder wires, typically of 0.02 inch diameter are susceptible to mechanical damages, such as bending, etc. A bent solder column cannot be loaded into the graphite fixture.
When filling high aspect ratio, i.e. higher than 4:1, via holes on semiconductor substrates, a screen printing technique was found ineffective and an injection molded solder (IMS) technique has been developed. For instance, U.S. Pat. No. 5,244,143, assigned to the common assignee of the present invention, discloses a new method for injecting molten solder directly into a mold, i.e. a graphite solder column mold. The patent further discloses the mold release and transfer methods for achieving low temperature solder column attach by the IMS technique. An improved injection molded solder technique, i.e. a vacuum injection molding technique was disclosed in a co-pending application that was assigned to the common assignee of the present invention under Ser. No. 08/518,874 which is incorporated herein by reference in its entirety. The vacuum injection molding method utilizes a pressure differential formed between either ambient and vacuum or positive pressure and vacuum. The method is carried out by utilizing a shallow vacuum link that allows a continuing evacuation of air from via holes that have a large aspect ratio, i.e. 5:1. The vacuum link must be sufficiently shallow such that the surface tension of molten solder prevents cross-leaking during the operation. The shallow link therefore effectively choke a significant part of the full pressure differential and thus producing only partial filling of via holes that have high aspect ratios.
It is therefore an object of the present invention to provide a method for forming an array of multi-alloy solder columns on an electronic substrate that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming an array of multi-alloy solder columns by first forming the solder columns with a high temperature solder and then joining the solder columns to an electronic substrate with a low temperature solder.
It is a further object of the present invention to provide a method for forming an array of multi-alloy solder columns by an injection molded solder technique wherein a high temperature molten solder is injected into a solder column mold plate equipped with a multiplicity of cavities.
It is another further object of the present invention to provide a method for joining a multiplicity of multi-alloy solder columns to an electronic substrate by utilizing an extraction plate, a mold plate and a transfer plate.
It is still another object of the present invention to provide a method for joining a multiplicity of multi-alloy solder columns to an electronic substrate by displacing a multiplicity of solder columns into a multiplicity of apertures in a transfer plate wherein the apertures are equipped with a flared opening such that a low temperature solder paste can be screen printed therein.
It is yet another object of the present invention to provide a method for joining a multiplicity of multi-alloy solder columns to an electronic substrate by forming the solder columns with a solder having a melting temperature higher than 240.degree. C. and joining the solder columns to an electronic substrate by a solder having a melting temperature lower than 240.degree. C.
It is still another further object of the present invention to provide an electronic substrate which has a multiplicity of solder columns electronically joined thereto that includes an electronic substrate having a multiplicity of bonding pads thereon and a multiplicity of solder columns each formed of a high temperature solder for bonding to the bond pads by a low temperature solder.
It is yet another further object of the present invention to provide an electronic substrate that has a multiplicity of solder columns electrically joined thereto wherein the solder columns are formed with a high temperature solder and joined to the electronic substrate with a low temperature solder.